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Committee Member Nagarajan Ranganathan, Ph. Committee Member Sanjukta Bhanja, Ph. Keywords behavioral synthesis, power-aware design, thermal analysis, interconnectcentric design, stochastic interconnect estimation, layout-aware synthesis.
- Low-Power High-Level Synthesis for Nanoscale CMOS Circuits.
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Abstract Aggressive scaling of nanoscale CMOS integrated circuits has created significant design challenges arising from increasing power densities, thermal concerns, and rising wire delays. Included in American Studies Commons.
High-Level Synthesis Fundamentals | SpringerLink
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ASPDAC '19- Proceedings of the 24th Asia and South Pacific Design Automation Conference
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